Released poco-DRAM and embedded controller

Overview

poco-apoco’s DRAM controller carries out the maximum bus efficiency by additional high-speed tRC DRAM and the intelligent control.  While the density and the I/O bandwidth are abundant resources in today’s DDR DRAM, its slow random-access often causes the system bottleneck.  The multi-bank architecture can alleviate the slow random-access, however it is still critical in the worst case application and also in case of more than four banks activation by tFAW (Four Activate Window) restriction. poco-apoco’s unique DRAM dramatically improves the random-access 2x as fast with keeping the identical package/pinout as those of JEDEC std. DRAM.  Thus, the users easily boost the operating bus efficiency by mean of apple-to-apple replacement without any tasks of expensive board re-design.

 

For more information, please check the following link (poco-DRAM-controller_STD).

 

ポコアポコネットワークス社によるメモリ(DRAM)コントローラは、ランダムアクセス性能を従来のJEDEC標準DRAMと比較して2倍高速化した当社製poco-DRAMを動作制御するものでFPGAをはじめSoC/ASICなどに実装するソフトウェアです。4バンク以上の動作のついての制限tFAW (Four Activate Window) が解消されたことと併せ、バス効率を大幅に向上しました。

 

詳細は以下のリンクを参照ください(和poco-DRAM-controller_STD)。