IP

DRAM controller IP

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Nowadays, DRAM is a reasonable market price memory due to its robust scale merit. On the contrary, its difficult timing restriction described in the component spec. often affects the system performance. Unfortunately, DRAM timing spec. is getting complicated more and more, and the design of DRAM controller is a key for the memory users.

poco-apoco Networks provides an evolutional DRAM controller to keep the best performance, and saves the engineering resource and the design time.

 

Product lineup

poco-DRAM2/3/3S for DDR2/DDR3/DDR3 fully compatible interface, respectively

Network Application IP

An example of network application IPs provides routing(FIB), Flow and access control list (ACL) and statistical table for the forensic purpose.

Product lineup

IP on FPGA and external single chip DDR DRAM performs

1M-entry times 512bit key at the frequency of 100M-lups.

Graphics/Data Processing IP

Based on the fast random access performance of poco-DRAM, we are developing graphics and data processing IP.

 

IP

DRAMコントローラIP

 当社の開発した高性能DRAM poco-DRAMのコントローラです。FPGAやSoCに搭載し、poco-DRAMとの組み合わせで、高速なランダムアクセス 性能を実現します。

ネットワーク向けIP

 Lookup Table、検索、routing、ACLといったネットワーク機器、技術に必要な機能を持つIPを提供します。外付けのpoco-DRAMとの組み合わせで1Mエントリーのセキュリティ用のリスト(ホワイトリスト)を実現することも可能です。

画像処理/信号処理IP

 高速ランダムアクセス性能を持つpoco-DRAMとの組み合わせで、高速な画像処理、データ処理が可能なIPを提供します。

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Please refer to the data sheet for more information.

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詳細はデータシートをご参照ください。

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