Technical Detail and More info.

Embedded IP core

Packet classification, FIB, Flow, ACL and others

An embedded IP described above provides CAM/TCAM compatible function,

e.g. 512bit key times 4K entry performed onto FPGA at 10Gbps wire-speed.

Also, its table size (entry size) is easily expanded (over 1M entry)

by optional external DDR DRAM

 

poco-DRAM

20161129_600

 

Major timing parameters comparison (example)

  JEDEC DDR3-800 poco-DRAM3S-800
CL-tRCD-tRP 5-5-5 [cycles] 5-4-4 [cycles]
CWL 5 [cycles] 4 [cycles]
tCK (min) 2.5 ns 2.5 ns
tWR (min) 15.0 ns 10.0 ns (4 cycles)
tRC (min) Read: 50.0ns (20 cycles)
Write: 62.5ns (25 cycles)
Read: 25.0 ns (10 cycles)
Write: 27.5 ns (11 cycles)
tRAS (min) Read: 37.5 ns (15 cycles)
Write: 50.0ns (20 cycles)
Read: 15.0 ns (6 cycles)
Write: 17.5 ns (7 cycles)
tRRD (min) 10 ns (4 cycles) 5 ns (2 cycles)
tCCD (min) 10 ns (4 cycles) 10 ns (4 cycles)
tRTP (min) 10 ns (4 cycles) 5 ns (2 cycles)